Senior Principal Physical Design Engineer

About the role

NXP is looking for a Senior Principal Physical Design Engineer in Leuven. As a key technical leader, you will drive and execute advanced physical design activities for complex SoC and IP blocks, helping to meet demanding performance, power and area targets for cutting-edge semiconductor products.

Key responsibilities

• Lead and execute physical design for large-scale digital designs from RTL to GDSII, including floor planning, power planning, place and route, clock tree synthesis, STA, formal verification, DRC and LVS.
• Drive and optimise design methodologies, flows and scripts to improve efficiency, turnaround time and design quality.
• Perform critical path analysis and propose solutions to meet aggressive frequency and power targets.
• Collaborate with design, architecture and verification teams to resolve complex technical issues.
• Mentor junior and mid-level engineers and foster their growth.
• Evaluate and integrate new EDA tools and technologies.
• Contribute to design specifications and architecture documents from a physical implementation viewpoint.
• Develop low-power techniques such as clock gating, power gating and multi-voltage design.
• Generate reports and documentation throughout the design cycle.

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering or a related field.
• 15+ years of ASIC physical design experience with a strong track record of successful tape-outs on advanced process nodes.
• Demonstrated ability to lead technical initiatives and mentor others.
• Excellent problem-solving, analytical and communication skills, able to work in a fast-paced team.

Required skills

• EDA tools: Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, Ansys RedHawk/PathFinder.
• Scripting: Tcl, Perl, Python.
• Static timing analysis, low-power design and DFM principles.