Physical ASIC Design Implementation Engineer (Backend P&R)

About the role

This contract position is based in Leuven, Belgium and focuses on full backend ASIC implementation from netlist‑in to GDSII‑out. You will work on a hybrid basis for a world‑renowned research and innovation hub, handling projects across technology nodes from N2 to 180 nm.

Key responsibilities

• Own end‑to‑end backend implementation projects using Cadence Innovus.
• Lead top‑level SDC partitioning and translate timing budgets into sub‑block constraints.
• Drive sign‑off closure for tape‑out in close collaboration with the physical design team.
• Act as the technical point of contact for customers, discussing specifications and managing future projects.

Required profile

• Proven expertise in the full Cadence Innovus place‑and‑route flow.
• Experience setting up flows for specific library sets and foundry nodes.
• Hands‑on experience with low‑power design (UPF) and SDC debugging.
• Strong knowledge of floorplanning, power‑grid design, CTS and routing.
• Ability to resolve setup and hold timing violations.

Required skills

• Cadence Innovus
• UPF (Unified Power Format)
• SDC (Synopsys Design Constraints)
• Floorplanning, power‑grid design, CTS, routing
• SPEF/Quantus extraction
• Tempus timing analysis
• Voltus power analysis
• Physical verification: DRC, ERC, LVS, ANT
• Logic equivalence checking